The present invention relates generally to sigma delta modulators. More specifically, a sigma delta modulator with a feedforward connection is disclosed.
Modern frequency synthesizers are sometimes implemented with a fractional N phase locked loop (PLL) to achieve more precise tuning of synthesized frequency. Many of these frequency synthesizers use sigma delta modulators (SDM) to produce the desired fractional values used in the circuitry.
FIG. 1 is a block diagram illustrating a frequency synthesizer with a fractional N phase locked loop and a sigma delta modulator. A reference frequency from a stable external source is input into a fractional N PLL 105. PLL 105 generates a voltage that is applied to a voltage controlled oscillator (VCO) 100. VCO 100 generates an output whose frequency depends on the VCO""s input voltage, and the output is fed back to PLL 105. The output frequency is divided by a multi-modulus divider 115 and sent to the rest of the PLL circuit. For the purposes of this example, details of the PLL relating to the multi-modulus divider are not shown. Modulus control 120 controls the value of the multi-modulus divider and varies the value over time.
Fractional division controller 110 supplies the values for A and B dividers. Initially, values NA and NB are sent to interface circuit 135. Another value, NK, is sent to SDM 140 to generate a randomized sequence that is used by interface circuit 135 to generate the values for A and B dividers. This sequence determines the rate at which a modulus in the multi-modulus divider is selected, and is proportional to NK. The A and B divider outputs are sent to modulus control 120, which sets the value in multi-modulus divider 115 accordingly. The multi-modulus divider value is in conjunction with the rest of the fractional N PLL circuit (not shown) to generate the desired voltage used by VCO 100 during the locking state. The locking frequency of the frequency synthesizer is related to the values of NA, NB, NK, modulus of multi-modulus divider 115, the reference frequency, and certain constants.
For the PLL to successfully lock with the desired frequency, the SDM should be stable. Also, the sequence generated by the SDM should not contain any spurious frequencies, i.e., the sequence should be as close to truly random as possible and not have any repeat patterns. It would be desirable to improve upon existing SDM designs to achieve good stability and randomization characteristics. Additionally, it would be useful to design the SDM with low in-band noise.